Verification Engineer Lead

Verification Engineer Lead Location: Barcelona, Spain (On-site) ️ Language Requirement: English (C1 minimum) Contract: Permanent – Internal team of our partner ️ Visa Sponsorship: Available Industry: Semiconductors, RISC-V, High-Speed Digital Design As a Verification engineer Lead, your role involves leading the Verification Team to guarantee the accuracy and functionality of intricate digital designs at the Register Transfer Level (RTL), adhering to specifications. You'll employ advanced verification techniques and tools to validate designs meticulously, ensuring their correctness and performance. Job description (responsibilities): - Team Leadership - Verification Planning - Testbench Development - Verification Environment Setup - Test Execution and Debugging - Coverage Analysis - Verification Methodologies Desired knowledge: - Experience leading a team - Proficiency in SystemVerilog and UVM - Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools - Experience with simulation and simulation tools - Knowledge of revision control methodology and tools (git, svn) - Experience in block level and sub-system or top level verification - Experience with formal and dynamic verification - Strong problem-solving skills and attention to detail - Excellent communication and teamwork abilities Preferred/Valued knowledge: - -Knowledge of RISC-V and RISC-V Vector Extension - -Experience with GLS - Knowledge of the JIRA tool - Experience with ASIC and FPGA design - -Knowledge of C++ Offered: Highly competitive salary. Opportunity to work within one of the most powerful teams in the industry, utilizing cutting-edge technologies. Visa sponsorship and relocation assistance provided, if necessary.

Location: Catalonia, ES

Posted Date: 8/19/2025