Physical Design Engineer

Job Description: Synthesis: Write synthesizable RTL code using Hardware Description Languages (HDLs) like Verilog or VHDL Perform logic synthesis using Electronic Design Automation (EDA) tools to optimize gate-level netlist for performance and area Analyze and debug synthesis reports to identify potential issues Formal Equivalence Verification (FEV): Utilize formal verification tools to ensure the functional equivalence of pre- and post-synthesis designs Write formal constraints and analyze verification results to identify potential design bugs Clock Tree Synthesis (CTS) / Clock Layout Planning (CLP): Design and implement clock trees to meet timing constraints and minimize skew Perform clock tree analysis using EDA tools to ensure signal integrity

Location: Greater Bengaluru Area, IN

Posted Date: 7/2/2025