Staff Physical Digital Design Engineer

Social network you want to login/join with: Staff Physical Digital Design Engineer, Barcelona Client: Monolithic Power Systems Location: Barcelona, Spain Job Category: Other EU work permit required: Yes Expiry Date: 02.06.2025 Job Description: Job Summary: We are looking for a Staff Physical Digital Design Engineer to join our team of Design Engineers in one of our offices in Europe. This role will be on-site; no remote option is available. The candidate will be responsible for all aspects of physical design and implementation. In this role, you will participate in the efforts of establishing physical design methodologies and flow automation. The Physical Design Engineer will be part of the design development team. The candidate will work on the digital design implementation and verification of mixed-signal ICs utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions. Essential Functions: Responsible for physical design, development, & verification of digital/mixed-signal ICs. Chip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closure. Work closely with the digital/analog design team for physical implementation and custom analog blocks/interface/IPs. Help build an automated environment for RTL-to-PNR using high-level languages and devops-like services. Qualifications: Requires an advanced degree in Electrical Engineering/Computer Science or equivalent. 7 years (preferred) of Physical Digital Design experience. 2 years (preferred) ASIC design, verification, or related work experience. Good written/verbal communication English skills and strong teamwork collaboration. Ability to work independently, follow instructions according to design specifications, and execute tasks to hit milestones with quality. Strong knowledge of ASIC development process and digital design techniques. Experience with programming, scripting, and automation languages like Perl/TCL/Unix. Strong technical abilities & understanding in these areas: Verilog/System Verilog coding, Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners, Multipower domain, signal integrity, & power/IR drop analysis, Linting and CDC requirements, Expertise in both hand-written and tool-driven functional/timing ECO, Physical Design Verification methodology to debug LVS/DRC issues at chip/block level, Industry physical tools: Cadence (preferred) or Synopsys, SOC design including uC design (ARM/RISCV), Digital on top designs using both bottom-up and top-down flows, Hierarchical STA for chip top designs, Advanced nodes below 16nm, FinFET. Experience with the following is desired: Statistical STA, AOCV, SI and noise analysis, Knowledge of power management industry/applications, I/F: I2C, SPI, USB, PMBUS, etc., Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, Object-oriented programming (Python, Java, etc.), VCS: git, svn, Devops, Continuous integration, continuous delivery, FPGA development: Xilinx (preferred), Intel, Lattice, etc. J-18808-Ljbffr

Location: barcelona, ES

Posted Date: 5/13/2025