Test Engineer

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer , you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross-functional teams, playing a key role in ensuring that designs are not only functional but thoroughly testable, production-ready, and robust. Key Responsibilities Drive the development and execution of DFT architectures, methodologies, and verification strategies. Implement hierarchical DFT, scan insertion, and ATPG compression techniques. Create and maintain STA DFT constraints and guide synthesis efforts for optimal test coverage. Collaborate closely with RTL design, IP integration, FPGA development, and physical design teams. Set up and run test pattern generation (ATPG) and debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or Mentor platforms). Solid understanding of RTL design , STA , and silicon test methodologies . A proactive, solution-oriented mindset and excellent collaboration skills. Please Note: You must currently be residing in the United Kingdom. For more information please contact Rachel Mason at IC Resources.

Location: Cambridge, GB

Posted Date: 5/12/2025