Principal Analog Design Engineer

Overview Principal Analog Design Engineer — Pavia, Italy. Salary: 85,000 to 110,000 plus bonus, signing bonus, and paid relocation. This role is a key position within our Optical PHY (CE-OPHY) team which is part of our Central Engineering division. Our team designs high-speed and optical transceivers for modern communication infrastructure, addressing the demand for bandwidth in mega data centers powering social media, video-on-demand, gaming, and other real-time data streams. We are committed to developing innovative first-to-market chips and subsystem solutions that push data rates and power efficiency. Key Responsibilities Design & Architecture: Analyze block specifications, own transistor-level design, and select suitable topologies. Design entire analog macros or IPs from concept to mass production. Verification & Validation: Model and validate circuit blocks; supervise layout activities, provide guidelines, and conduct post-layout verifications to ensure design integrity. Collaboration & Leadership: Work closely with other engineering teams, participate in cross-functional meetings, and train/mentor junior designers to build collective expertise. Project Management: Manage pre-silicon tasks (simulation and modeling) and post-silicon tasks (lab characterization, debugging, correlating measurements to simulations) through to high-volume production. Candidate Profile We are seeking a seasoned engineer with a deep background in analog IC design and a passion for pushing technological limits. Education & Experience A Masters degree or Ph.D. in Electrical Engineering or a related field is required, with 12-15 years of professional experience. Technical Skills You must have proven experience in designing ICs from architecture definition through lab characterization and volume production. Solid experience in analog design, preferably in the multi-GHz range, is essential. Proficiency in supervising custom analog layout using standard EDA CAD tools and debugging designs to correlate simulations with measurements is required. Preferred Qualifications Experience with multi-Gbps electrical SerDes or electro-optical transceivers is highly desirable. Knowledge of advanced CMOS nodes including FinFET would be advantageous. Personal Skills Strong communication, presentation, and documentation skills. Given our international team and location, proficiency in both written and spoken Italian and English (minimum B2 level) is required. Work Model This is an on-site, full-time position located in Pavia, Italy. Experience Staff IC Employment Type Full-Time Vacancy 1 Salary Monthly Salary: 75,000 - 110,000 J-18808-Ljbffr

Location: Pavia, Lombardia, IT

Posted Date: 11/11/2025